1. Field of the Invention
The present invention relates to a layout design method of a semiconductor integrated circuit and a layout design tool of a semiconductor integrated circuit.
2. Description of Related Art
A demand for high performance, downsizing, and lower power consumption in a semiconductor integrated circuit including LSI (Large Scale Integration) which uses MOS (Metal Oxide Semiconductor) transistor has been increasing in recent years in order to achieve advanced data processing. However, a process technology for a semiconductor integrated circuit becomes narrower in order to achieve the high performance and the downsizing, a driving voltage for a semiconductor integrated circuit becomes lower. Accordingly a threshold voltage of a transistor decreases and a leak current in off state of a transistor increases. Consequently it is difficult to reduce the power consumption of a semiconductor integrated circuit.
To resolve this problem, there is known a method that forms a well region that is electrically separated from a semiconductor substrate, sets a potential of the well region different from a potential of a substrate, and increases a threshold voltage superficially. However separating a well potential in this way brings the following issue. To form a P well of a different potential from a substrate potential in a P type semiconductor substrate, an N well needs to be formed in a P type substrate and further a P well needs to be formed in the N well. Accordingly a region where a devices are formed in a substrate and a region (a separating well region) where devices are formed in a well that is electrically separated from the substrate are formed in the semiconductor substrate.
A method of forming a separating well region in the abovementioned way is disclosed in Japanese Unexamined Patent Application Publication No. 11-191593. FIG. 10 is a schematic view showing a semiconductor integrated circuit disclosed in Japanese Unexamined Patent Application Publication No. 11-191593. As shown in FIG. 10, a P well 302a and an N well 304a are electrically separated from a P type substrate by N type well separating regions 308a and 308b. A potential supplied to the P type substrate and a potential supplied to the P well 302b formed over the P type substrate are different. As described in the foregoing, the P well 302a and the N well 304a can be treated as separating regions. A method of automatically forming a mask pattern data of a semiconductor integrated circuit is disclosed in Japanese Unexamined Patent Application Publication No. 11-191593. This reduces design time and also improves design quality.
FIG. 11 is a flow chart showing a layout design of a semiconductor integrated circuit according to Japanese Unexamined Patent Application Publication No. 11-191593. Firstly a region where a basic cell is placed to be is specified using wafer process information 1, IC logic information 2, and cell/core information 3 that is input to a layout design tool (ST1). A cell is comprised of MOS transistors. Further, a cell is a basic element to form a semiconductor integrated circuit. A basic cell refers to a cell placed in a region having the same potential as of a substrate potential.
After that, the basic cell is automatically placed in ST2. And then, basic cell is automatically wired to another basic cell so as to form a circuit in ST3. In ST4, a well separating region is placed around a cell in a separating well region and a wiring connection for power supply is automatically generated. Lastly, the layout is verified in ST5.
However, there is a latter mentioned problem in designing a semiconductor integrated circuit having a separating well region using a flow shown in FIG. 10. The problem is that the method conducts a process of ST4 separately from a process of ST1 to ST3. Thus another process is required to form the separating well region and to connect a power supply of the separating well region.
Further, an interval between basic cells placed in the substrate potential region and the separating well region inserted later may not satisfy a design standard. In such case, the semiconductor integrated circuit needs to be redesigned. This increases processes and design time. Further, to insert a separating well region later, a design process of a semiconductor integrated circuit is complicated. This will require a skilled designer and also could deteriorate design quality due to design error.
Moreover, the step ST4 is not needed in a case using the flow chart of FIG. 10 for designing a semiconductor integrated circuit that does not have the separating well region. Accordingly this creates design time more than necessary.